1. Field of the Invention
The present invention relates to semiconductor devices and other electronic components and, more particularly, to the use of tin containing lead free and reduced lead solder interconnects in the devices and to the removal of adherent metal layers used in the interconnect fabrication process without damaging the solder interconnects or the underlying component structure and with a high electronic component yield.
2. Description of Related Art
C4 is an advanced microelectronic chip packaging and connection technology. “C4” stands for Controlled Collapse Chip Connection. C4 is also known as “solder bump”, “solder balls” and “flip chip” and these terms may also be used in conjunction such as “C4 solder bump”.
The basic idea of C4 is to connect chips (semiconductor devices), chip packages, or such other electronic component units by means of solder bumps between two surfaces of the units. These tiny bumps of electrically conductive solder bridge the gaps between respective pairs of metal pads on the units being connected. Each pad has a corresponding pad on the other unit's surface; the pad arrangements are mirror images. As the units are pressed together and heated the solder bumps on the pads of the first unit are contacted with corresponding conductive pads (having no bumps) on the second unit and reflowed, partially collapsing the solder bumps and making connections between respective pads.
In C4 the solder bumps are formed directly on the metal pads of the one unit. The pads are electrically isolated from other components by the insulating substrate that surrounds each pad. The substrate might be silicon (Si) or some other material. The bottom of the pad is electrically connected into the chip circuit and a major application of C4 is in joining chips to a carrier or package.
One method of forming solder bumps uses sputtering or vacuum deposition. In this method, solder metal is evaporated in a vacuum chamber. The metal vapor coats everything in the chamber with a thin film of the evaporated metal. To form solder bumps on the substrate, the vapor is allowed to pass through holes in a metal mask held over the substrate. The solder vapor passing through the holes condenses onto the cool surface into solder bumps.
An alternative technique for making solder bumps is electrodeposition, also called electrochemical plating or electroplating. This method also uses a mask and forms solder bumps only at the selected sites, but the technique is very different from the evaporation method.
The first step in electrolytically forming C4 solder bumps is to deposit a continuous stack of metal films across the wafer to be bumped. This so-called “seed layer” performs a dual function. First, it provides a conductive path for current flow during the electrolytic deposition of the solder bumps. Second, it remains under the solder bumps and forms the basis for the ball limiting metallurgy (BLM) for the C4s. Therefore, it must contain at least one layer that is conductive enough to permit uniform electrodeposition across the entire expanse of the wafer. The bottom layer must adhere well to the underlying semiconductor device passivation and the top layer must interact sufficiently with the solder to form a reliable bond. In addition, the BLM may contain barrier layers which prevent the solder from detrimentally interacting with the underlying device constituents. Finally, the stresses generated by the composite stack should be low enough to sustain the reliability of the C4 joint throughout various thermal and mechanical stresses. Considering all of these factors, seed layers often consist of more than one metal layer, and these various layers must be etched away from between the C4s at some point during the processing in order to electrically isolate the interconnects.
The second step, after the seed layer is laid down, is to form a mask by photolithography. A layer of photoresist is laid onto the seed layer and exposed to light. The mask has rows of holes where the solder bumps are to be deposited.
The third step is electrodeposition (electroplating) of solder into the mask holes.
After the solder bumps are formed, the mask of cured photoresist is removed. The substrate now is covered with the continuous seed layer and numerous solder bumps. Then, the seed layer is removed in between the solder bumps to electrically isolate them by suitable wet etching and/or electroetching processes.
The solder typically used for the C4 solder bumps is 95-97 weight percent Pb and 3-5 weight percent Sn. A typical seed layer could comprise a lower barrier layer containing Ti or Ta such as TiW, a phased Cr/Cu layer or a Cr/Cu alloy and an upper Cu layer. The process utilized to simultaneously remove the Cr/Cu and Cu layers is typically an electroetching process which includes an aqueous solution containing glycerol, potassium phosphate and potassium sulfate as disclosed in U.S. Pat. No. 6,468,413, which patent is hereby incorporated by reference. The lower barrier layer is then etched using a wet etching process which includes an aqueous etchant as also disclosed in U.S. Pat. No. 6,468,413.
More recent applications use a lower melting solder for the C4 bumps to enable lower temperature chip joining. Such a lower melting solder could be the lead/tin solder composition comprising 63 weight percent Sn and 37 weight percent Pb.
Cotte et al. U.S. Pat. No. 5,800,726, the disclosure of which is incorporated by reference herein, have proposed an aqueous solution for the wet etching of various metals, such as TiW, in the presence of eutectic solder. This solution comprises potassium phosphate, hydrogen peroxide, EDTA and oxalic acid.
There is also a growing need to use lead free and reduced lead solder interconnects and these solders typically employ Sn and small concentrations of one or more other metals such as Ag, Cu and Bi. These solders are especially high in tin, containing 95-99% Sn. Seed layer removal with high Sn solders is more difficult than the standard lead solders (such as 97/3 Pb/Sn). For example, in a typical seed layer such as TiW/Cu/Cr/Cu, when using an electroetch to remove the Cu/Cr/Cu seed layers, this highly oxydizing environment promotes the formation of Sn oxides and other Sn compounds near the solder bump and over the TiW underlying surface. The Sn oxide masks the underlying layer leaving a conductive residue between the interconnects. This affects the yield of the interconnection fabrication process since residual metal between the interconnects may cause shorting and other related failures in the device.
Bearing in mind the problems and deficiencies of the prior art it is an object of the present invention to provide an effective and high yield method to remove the seed layer during the interconnect fabrication process used to make electronic components such as semiconductors without damaging the interconnects and underlying electronic component substrate.
A further object of the invention is to provide an effective and high yield method to remove the seed layer during the interconnect fabrication process when using lead free and reduced lead solder interconnects, especially high tin solders, without damaging the interconnects and underlying electronic component substrate.
Another object of the present invention is to provide an effective and high yield method to remove the seed layer during the interconnect fabrication process using an electroetch process to remove seed layers overlying a barrier sublayer such as TiW without damaging the interconnects and underlying substrate.
These and other purposes of the present invention will become more apparent from the following description considered in conjunction with the following drawings.